</a>DVD" title="DVD">DVD" title="DVD">DVD,STB,音頻設(shè)備,打印機(jī),外部存儲(chǔ)設(shè)備和其它配備了USB的設(shè)備.本文介紹了R8A66597主要特性,引腳功能框圖以及評估板R0K866597D020BR主要特性,電路圖,材料清單和PCB元件布局圖.
The R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed, Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral Controller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification Revision 2.0.
This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification Revision 2.0.
The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer.
R8A66597主要特性:
1. Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB
• Built-in USB Host Controller and Peripheral Controller
• Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register
• Built-in USB transceiver
2.Low power consumption
• 1.5V core power consumes less power when operating
• With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is also applicable for portable devices
• Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the USB function.
• Operational with a 3.3V single power supply using the internal 1.5V core power regulator
3.Space-saving package
• Few external devices and space-saving package
?? VBUS signal can be connected directly to the controller input pin
?? Built-in D+ pull-up resistor (for Peripheral function)
?? Built-in D+ and D- pull-down resistors (for Host function)
?? Built-in D+ and D- terminating resistors (for Hi-Speed operations)
?? Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations)
4.Compatible with all USB transfer types
• Compatible with all USB transfer types, including isochronous transfer
?? Control transfer
?? Bulk transfer
?? Interrupt transfer (not compatible with high-bandwidth)
?? Isochronous transfer (not compatible with high-bandwidth)
5. Bus interface
• 16-bit CPU bus interface
?? Compatible with 16-bit separate bus/16-bit multiplex bus
?? Compatible with DMA transfer in 8-bit/16-bit access (slave function)
• 8-bit split bus (exclusive for external direct memory access controller (DMAC)) interface
• Built-in two DMA interface channels
• DMA transfer provides 40MB/second high-performance data transfer
6.Pipe configuration
• Built-in 8.5KB buffer memory for USB communication
• Maximum of ten pipes can be selected (including default control pipe)
• Programmable pipe configuration
• Any endpoint address can be assigned to Pipe1 to Pipe9
• Transfer conditions that can be written for each pipe
?? Pipe0: Control transfer, single buffer fixed at 256 bytes
?? Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes.
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
?? Pipe3~Pipe5: Bulk transfer, continuous transfer modes,programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
?? Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes
7. Features when selecting Host functions
• Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps)
• Several Peripheral devices can be connected through one tier hub
• Reset handshake auto response
• SOF and packet transmission schedule automation
• Transfer interval setup function for Isochronous and Interrupt transfer
8.Features when selecting Peripheral functions
• Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps)
• Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response
• Control transfer stage management function
• Device state management function
• Auto response function related to SET_ADDRESS request
• NAK response interrupt function (NRDY)
• SOF interpolation function
9.Functions that Provide On-The-Go Support
• Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up
• Built-in control bit facilitates Host Negotiation Protocol
10.Other functions
• Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function
• Transfer end function according to transaction count
• End function of DMA transfer by external trigger (DEND pin)
• SOF plus output function
• Three types of input clock can be selected by built-in PLL
?? Select from 48MHz/24MHz/12MHz
• Function to modify the BRDY interrupt event notification timing (BFRE)
• Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM)
• Function to provide the auto clock from clock stop status
• NAK setting function (SHTNAK) for PID response corresponding to transfer end
R8A66597主要應(yīng)用:
Navigation systems, DVD recorders, set-top boxes, audio devices, printers, external storage devices and other devices equipped with USB.
The R0K866597D020BR is the evaluation board of the USB Host function and built-in functions. This instruction manual explains how to setup up and operate the related hardware and offers cautionary notes concerning usage.
圖1.R8A66597引腳功能框圖
R8A66597評估板R0K866597D020BR
The R0K866597D020BR is an evaluation board for the Renesas Hi-Speed USB ASSP R8A66597FP. Two USB-A receptacles are mounted on the board for evaluation of USB host operations using USB port0 and USB port1 of R8A66597. CN1 can be used for evaluation of USB peripheral operations. Please refer to the data sheet “USB2.0 Dual
Function Controller R8A66597FP” for detailed specifications of the R8A66597.
評估板R0K866597D020BR主要特性:
(1) By connecting this board to a control board using the interface connector of this board, it is possible to evaluate the user system.
(2) A solder pattern is prepared on the USB signal lines for chip common mode choke coils. It is possible to do EMI suppression evaluation.
(3) A solder pattern is prepared on the USB signal lines for ESD protection devices. It is possible to do ESD protection evaluation.
(4) It is possible to supply 3.3V or 1.8V to the interface power VIF of R8A66597FP.
(5) It is possible to test R8A66597FP’s functions (excluding split bus) by connecting with Renesas Starter Kits board.
It is possible to supply 5V, 500mA to the VBUS.
圖2.評估板R0K866597D020BR外形圖
圖3.評估板R0K866597D020BR電路圖
評估板R0K866597D020BR材料清單(BOM):
圖4.評估板R0K866597D020BR PCB元件布局圖(頂層)
圖5.評估板R0K866597D020BR PCB元件布局圖(底層)
詳情請見:
http://am.renesas.com/media/products/tools/introductory_evaluation_tools/starterkits_evaluation_boards/R8A66597/rej03f0229_r8a66597ds.pdf
和
http://am.renesas.com/media/products/tools/introductory_evaluation_tools/starterkits_evaluation_boards/R8A66597/r19an0005ej_66597d020.pdf
The R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed, Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral Controller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification Revision 2.0.
This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification Revision 2.0.
The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer.
R8A66597主要特性:
1. Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB
• Built-in USB Host Controller and Peripheral Controller
• Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register
• Built-in USB transceiver
2.Low power consumption
• 1.5V core power consumes less power when operating
• With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is also applicable for portable devices
• Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the USB function.
• Operational with a 3.3V single power supply using the internal 1.5V core power regulator
3.Space-saving package
• Few external devices and space-saving package
?? VBUS signal can be connected directly to the controller input pin
?? Built-in D+ pull-up resistor (for Peripheral function)
?? Built-in D+ and D- pull-down resistors (for Host function)
?? Built-in D+ and D- terminating resistors (for Hi-Speed operations)
?? Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations)
4.Compatible with all USB transfer types
• Compatible with all USB transfer types, including isochronous transfer
?? Control transfer
?? Bulk transfer
?? Interrupt transfer (not compatible with high-bandwidth)
?? Isochronous transfer (not compatible with high-bandwidth)
5. Bus interface
• 16-bit CPU bus interface
?? Compatible with 16-bit separate bus/16-bit multiplex bus
?? Compatible with DMA transfer in 8-bit/16-bit access (slave function)
• 8-bit split bus (exclusive for external direct memory access controller (DMAC)) interface
• Built-in two DMA interface channels
• DMA transfer provides 40MB/second high-performance data transfer
6.Pipe configuration
• Built-in 8.5KB buffer memory for USB communication
• Maximum of ten pipes can be selected (including default control pipe)
• Programmable pipe configuration
• Any endpoint address can be assigned to Pipe1 to Pipe9
• Transfer conditions that can be written for each pipe
?? Pipe0: Control transfer, single buffer fixed at 256 bytes
?? Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes.
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
?? Pipe3~Pipe5: Bulk transfer, continuous transfer modes,programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
?? Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes
7. Features when selecting Host functions
• Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps)
• Several Peripheral devices can be connected through one tier hub
• Reset handshake auto response
• SOF and packet transmission schedule automation
• Transfer interval setup function for Isochronous and Interrupt transfer
8.Features when selecting Peripheral functions
• Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps)
• Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response
• Control transfer stage management function
• Device state management function
• Auto response function related to SET_ADDRESS request
• NAK response interrupt function (NRDY)
• SOF interpolation function
9.Functions that Provide On-The-Go Support
• Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up
• Built-in control bit facilitates Host Negotiation Protocol
10.Other functions
• Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function
• Transfer end function according to transaction count
• End function of DMA transfer by external trigger (DEND pin)
• SOF plus output function
• Three types of input clock can be selected by built-in PLL
?? Select from 48MHz/24MHz/12MHz
• Function to modify the BRDY interrupt event notification timing (BFRE)
• Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM)
• Function to provide the auto clock from clock stop status
• NAK setting function (SHTNAK) for PID response corresponding to transfer end
R8A66597主要應(yīng)用:
Navigation systems, DVD recorders, set-top boxes, audio devices, printers, external storage devices and other devices equipped with USB.
The R0K866597D020BR is the evaluation board of the USB Host function and built-in functions. This instruction manual explains how to setup up and operate the related hardware and offers cautionary notes concerning usage.
圖1.R8A66597引腳功能框圖
R8A66597評估板R0K866597D020BR
The R0K866597D020BR is an evaluation board for the Renesas Hi-Speed USB ASSP R8A66597FP. Two USB-A receptacles are mounted on the board for evaluation of USB host operations using USB port0 and USB port1 of R8A66597. CN1 can be used for evaluation of USB peripheral operations. Please refer to the data sheet “USB2.0 Dual
Function Controller R8A66597FP” for detailed specifications of the R8A66597.
評估板R0K866597D020BR主要特性:
(1) By connecting this board to a control board using the interface connector of this board, it is possible to evaluate the user system.
(2) A solder pattern is prepared on the USB signal lines for chip common mode choke coils. It is possible to do EMI suppression evaluation.
(3) A solder pattern is prepared on the USB signal lines for ESD protection devices. It is possible to do ESD protection evaluation.
(4) It is possible to supply 3.3V or 1.8V to the interface power VIF of R8A66597FP.
(5) It is possible to test R8A66597FP’s functions (excluding split bus) by connecting with Renesas Starter Kits board.
It is possible to supply 5V, 500mA to the VBUS.
圖2.評估板R0K866597D020BR外形圖
圖3.評估板R0K866597D020BR電路圖
評估板R0K866597D020BR材料清單(BOM):
圖4.評估板R0K866597D020BR PCB元件布局圖(頂層)
圖5.評估板R0K866597D020BR PCB元件布局圖(底層)
詳情請見:
http://am.renesas.com/media/products/tools/introductory_evaluation_tools/starterkits_evaluation_boards/R8A66597/rej03f0229_r8a66597ds.pdf
和
http://am.renesas.com/media/products/tools/introductory_evaluation_tools/starterkits_evaluation_boards/R8A66597/r19an0005ej_66597d020.pdf
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