摘要:

ADM3052在CAN協(xié)議控制器與物理層總線之間創(chuàng)建一個(gè)隔離接口。它能以最高1Mbps的數(shù)據(jù)速率工作。該器件的總線引腳（V+、V−、CANH和CANL）集成有接線錯(cuò)誤保護(hù)功能。本方案可以快速開發(fā)ADM3052應(yīng)用。

基本特征：

5 kV rms 隔離式CAN收發(fā)器

集成V+線性調(diào)節(jié)器

總線側(cè)由V+和V−供電

工作電壓（V+）：11 V至25 V

工作電壓(V_DD1：5V或3.3V

符合ISO 11898標(biāo)準(zhǔn)

最高1Mbps 高速數(shù)據(jù)傳輸率

總線引腳提供短路保護(hù)

集成總線接線錯(cuò)誤保護(hù)

無電節(jié)點(diǎn)不干擾總線

總線支持110個(gè)或更多節(jié)點(diǎn)

方案特點(diǎn)：

 The EVAL-ADM3052EBZ allows the ADM3052 isolated CAN transceiver to be quickly and easily evaluated. The evaluation board allows all of the input and output functions to be exercised without the need for external components.

On the EVAL-ADM3052EBZ, the power is isolated between a single 3.3 V or 5 V supply on VDD1, the logic side, and a single 24 V supply provided on V+, the bus side. R1, the 300 Ω external resistor, is used by the built-in linear regulator to share the power dissipation between R1 and the internal die to reduce the internal heat dissipation in the package.

The bus voltage sense pin (V+SENSE), detects when V+ is connected on the bus side. A low on V+SENSE indicates that power is available on the bus side, and a high on V+SENSE indicates that power is absent from the bus side.

VDD1 is the power supply of the logic side. A 22 μF decoupling capacitor, C5, is fitted between VDD1 and GND1. A capacitor of 1 μF is fitted on the CINT pin. A 100 nF capacitor, C6, is fitted between V+ and V−, and a 10 μF capacitor, C7, is fitted between V+R and V−.

An example operation of the EVAL-ADM3052EBZ is shown in Figure 3. Connect a signal generator on TXD and set up a 500 kHz square wave clock with output swing between 0 V and 5 V. Connect the scope probes to the CANH and CANL test points. A plot of the oscilloscope for TXD, CANH, and CANL is shown in Figure 2. Channel 1 shows the TXD signal, and Channel 2 and Channel 3 show the CANH and CANL signals, respectively.

原理圖：
 
           
原理圖1
                        
PCB layout