雖然片上ESD結(jié)構(gòu)被用作極好的次要保護(hù)，但是它們通常對(duì)長(zhǎng)期暴露在自由環(huán)境下的接口保護(hù)不足。
“模擬域”部分將焦點(diǎn)放在IC、子系統(tǒng)和系統(tǒng)設(shè)計(jì)者面對(duì)的不斷增長(zhǎng)的電路設(shè)計(jì)挑戰(zhàn)：接口ESD保護(hù)。沿著工業(yè)現(xiàn)有技術(shù)的軌跡，接口保護(hù)難度按兩個(gè)趨勢(shì)日益增加。首先，增加了處理速度和功能密度的需求，推動(dòng)IC制造者進(jìn)一步縮減MOS裝置的最小尺寸。對(duì)給定的門絕緣體，設(shè)備原理上需要維持絕緣體厚度與橫向尺寸成比例（參考文獻(xiàn)1）。然而，較薄的絕緣體更容易受ESD的影響。
其次，端口速度持續(xù)增加，特別是便攜式多媒體設(shè)備的興起。例如，1996年發(fā)布的USB 1.0提供12Mbps的接口。四年后，USB 2.0達(dá)到480 Mbps。今年Intel開發(fā)者論壇出現(xiàn)，但仍未發(fā)布的USB 3.0，用平行光纖電纜替代銅連接器達(dá)到4.8Gbps的連接速度。IEEE 802.3（以太網(wǎng)）和IEEE 1394（火線）或多或少顯示了趨勢(shì)。
傳統(tǒng)上，包括ESD分流結(jié)構(gòu)，帶標(biāo)準(zhǔn)互連焊盤單元的IC保護(hù)內(nèi)部電路，避免ESD沖擊設(shè)備引腳。如果其結(jié)構(gòu)連接嚴(yán)格的抗ESD處理程序，對(duì)制造商而言，片上ESD保護(hù)板裝配的IC安全是必要
的。雖然片上ESD結(jié)構(gòu)被用做極好的次要保護(hù)，但是它們通常對(duì)長(zhǎng)期暴露在自由環(huán)境下的接口保護(hù)不足。
這些結(jié)構(gòu)不足的原因有兩部分：它們太小到不能吸收接口常出現(xiàn)的瞬態(tài)大能量，遠(yuǎn)離接口入口點(diǎn)放置，防止鄰近軌跡的耦合。一旦I/O線的片上ESD單元開始工作，瞬態(tài)電流沿走線增加，引起走線感應(yīng)，產(chǎn)生相應(yīng)瞬態(tài)電壓，Ldi/dt。鄰近I/O走線的互感導(dǎo)體滿足超過(guò)其自身片上ESD單元容量的瞬態(tài)現(xiàn)象。這些鄰近軌跡包括時(shí)鐘、數(shù)據(jù)或其他非端口信號(hào)（參考文獻(xiàn)2）。
裝配TVS（瞬態(tài)電壓干擾抑制器）到與入口點(diǎn)盡可能近，通過(guò)瞬態(tài)電流進(jìn)入產(chǎn)品前分流ESD到地，來(lái)減少問(wèn)題。這樣做，用最小的附加費(fèi)用，充分地增加了產(chǎn)品的魯棒性。“如果手指接近節(jié)點(diǎn)，保護(hù)它”是一個(gè)好準(zhǔn)則。盡管鍵帽是絕緣的，這個(gè)準(zhǔn)則也應(yīng)用到鍵區(qū)開關(guān)線。
高速接口需要帶特殊低旁路電容的TVS。檢查銷售商的產(chǎn)品線，特別是高速接口設(shè)備。如果不能找到設(shè)備的特定接口，與銷售商明確提供的標(biāo)準(zhǔn)接口比較信號(hào)頻率和源線特性?？紤]TVS制造商的要求，確保理解特定設(shè)備的ESD源模型。例如，JEDEC HBM（人體模型）通過(guò)1.5kΩ resistor，使用100pF電容放電。測(cè)試模型的可重復(fù)性結(jié)果歷史上就是關(guān)注區(qū)域（參考文獻(xiàn)3）。IEC-61000-4-2標(biāo)準(zhǔn)的測(cè)試方法提升了可重復(fù)性，其源模型——150Ω后的150pF——使設(shè)計(jì)要求更苛刻。
英文原文：
Protecting interfaces from ESD
Though on-chip-ESD structures serve as excellent secondary protection, they are usually insufficient to protect an interface over years of exposure in uncontrolled environments.
By Joshua Israelsohn, Contributing Technical Editor -- EDN, 12/3/2007
This installment of “Analog Domain” focuses on one of the growing circuit-implementation challenges that confronts IC, subsystem, and system designers alike: interface ESD protection. Two trends make interface protection increasingly difficult as we move along our industry’s current technology trajectory. First, increasing demands for processing speed and functional density have pushed IC fabricators to shrink further the minimum dimensions of MOS devices. For a given gate dielectric, device physics require maintaining the dielectric thickness in proportion to lateral dimensions (Reference 1). Thinner dielectrics, however, are more susceptible to ESD overstress.
Second, port speeds continue to increase, particularly with the growing success of portable-media devices. As one example, the 1996 USB 1.0 release provided for 12-Mbps interfaces. Four years later, a USB 2.0 feed could reach 480 Mbps. The yet-unreleased USB 3.0, shown at this year’s Intel Developer Forum, trades copper interconnect for parallel fiber-optic cable to attain a 4.8-Gbps connection. IEEE 802.3 (Ethernet) and IEEE 1394 (Firewire) show the trend to a greater or lesser degree.
Traditionally, ICs include ESD-shunting structures within their standard interconnect-pad cells, which protect the internal circuitry from ESD strikes to the device’s pins. The on-chip-ESD protection may be all that’s necessary to see an IC safely from its manufacturer to a board assembler if both organizations adhere to strict anti-ESD-handling procedures. Though on-chip-ESD structures serve as excellent secondary protection, however, they are usually insufficient to protect an interface over years of exposure in uncontrolled environments.
The reasons these structures are insufficient are twofold: They are too small to absorb large energy transients that interfaces commonly experience in the field, and they reside too far away from the interface-entry point to prevent coupling to adjacent traces. Once an I/O line’s on-chip-ESD cell begins to conduct, a current transient develops along its trace, exciting the trace’s inductance, causing a corresponding voltage transient, Ldi/dt. Adjacent conductors with mutual inductance to the I/O trace see coupled transients that can exceed the capabilities on their own on-chip-ESD cells. These adjacent traces can include clock, data, or other nonported signals (Reference 2).
Mounting TVSs (transient-voltage suppressors) as close to the entry point as possible alleviates this problem by shunting the ESD event to ground before transient currents develop inside your product. Doing so can add substantially to your product’s robustness with minimal additional cost. “If a finger can get close to a node, protect it,” is a good rule of … errrrr … thumb. This rule applies to keypad switch lines, too, despite their insulating keycaps.
High-speed interfaces require TVSs with particularly low shunt capacitances. Check your vendor’s product line for devices built for specific high-speed interfaces. If you don’t find devices specifically for your interface, compare your signalin
g frequencies and source-and-line characteristics with those of interface standards that the vendor explicitly supports. When considering TVS manufacturers’ claims, be sure to understand which ESD source model they use when specifying their devices. The JEDEC HBM (human-body model), for example, uses a 100-pF capacitor discharging through a 1.5-kΩ resistor. The repeatability of the test method’s results has been historically an area of concern (Reference 3). The IEC-61000-4-2 standard’s test method promotes repeatability, and its source model—150-pF behind 150Ω—is more demanding of your design.
References
Sicard, Etienne and Syed Mahfuzul Aziz, “Application note on 45-nm technology,” Institut National des Sciences Appliquées de Toulouse, June 27, 2007.
“Disadvantage of on-chip transient protection,” Application Note SI97-04, Semtech, September 2000.
Verhaege, Koen, et al, “Recommendations to further improvements of HBM ESD component level test specifications,” Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, September 1996.