中圖分類號(hào)： TN952 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.229987 中文引用格式： 阮成肖. 基于FPGA的雷達(dá)A式顯示電路設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022，48(8)：24-28. 英文引用格式： Ruan Chengxiao. Design of radar A-display circuit based on FPGA[J]. Application of Electronic Technique，2022，48(8)：24-28.
Design of radar A-display circuit based on FPGA
Ruan Chengxiao
Jiangsu Automation Research Institute，Lianyungang 222061，China
Abstract： In order to optimize and upgrade radar display technology, a radar A-display circuit based on FPGA is designed and implemented in this paper. The FPGA integrated radar display IP core is used to realize the sampling, processing and displaying of radar front-end signals. The design takes advantage of the huge programmable logic unit of the FPGA chip. The rich mature IP cores realize the functions of receiving, sampling, transforming and displaying the radar input signal of the single-chip logic chip. It simplified the hardware structure of the previous radar display system, reduced the display delay of the signal, and improved the radar display performance. At the same time, the design can realize other radar display methods by further modifying the internal IP core, so that it has the versatility and scalability of hardware devices.
Key words : FPGA；IP core；radar video；display technology
