中圖分類號：TP039 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234404
中文引用格式： 楊龍飛，盧仕，彭曠. 基于流水線的RSA加密算法硬件實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2024，50(1)：66-70.
英文引用格式： Yang Longfei，Lu Shi，Peng Kuang. Hardware implementation of RSA encryption algorithm based on pipeline[J]. Application of Electronic Technique，2024，50(1)：66-70.

Hardware implementation of RSA encryption algorithm based on pipeline

Abstract： To address the high cost of implementing long-bits RSA encryption algorithms in hardware, improvements have been made to the traditional radix-4 Montgomery algorithm. Firstly, a Carry-Save Adder (CSA) is introduced to efficiently complete large numbers of addition computations. Optimization is then carried out in post-processing to reduce the number of large numbers to be calculated at each Montgomery computation. Finally, a pipelining technique is incorporated into the RSA encryption algorithm for parallel execution, thereby reducing the use of hardware resources. Experimental results on a Xilinx XC7K410T FPGA development board demonstrate that while maintaining encryption speed, the hardware resources used by the improved RSA encryption algorithm are only half of those of the previous parallel structure and can operate at higher frequencies.

Key words : RSA encryption；Montgomery algorithm；FPGA hardware implementation；pipeline