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基于FPGA的萬兆以太網(wǎng)UDP協(xié)議通信接口設(shè)計(jì)
2022年電子技術(shù)應(yīng)用第10期
趙世超,左金印,魏 驍,趙 哲
華北計(jì)算機(jī)系統(tǒng)工程研究所,北京100083
摘要: 針對(duì)嵌入式設(shè)備迅速增長的數(shù)據(jù)傳輸需求,介紹了一種依托于現(xiàn)場(chǎng)可編程門陣列(Field Programmable Gate Array,F(xiàn)PGA)平臺(tái),以光纖為傳輸媒介的萬兆UDP/IP協(xié)議通信接口模塊,并探究引入分支預(yù)測(cè)機(jī)制對(duì)通信接口模塊發(fā)送時(shí)延產(chǎn)生的影響。通過對(duì)現(xiàn)有網(wǎng)絡(luò)接口層、網(wǎng)際層、傳輸層和應(yīng)用層典型傳輸模型的深入研究,使用硬件描述語言,模塊化設(shè)計(jì)ARP控制器、IP控制器和UDP控制器,實(shí)現(xiàn)完備的UDP/IP通信接口模塊,并評(píng)估了引入分支預(yù)測(cè)機(jī)制對(duì)通信接口模塊發(fā)送時(shí)延產(chǎn)生的影響。分析表明:該設(shè)計(jì)實(shí)現(xiàn)簡(jiǎn)單,適配嵌入式設(shè)備對(duì)高帶寬、低延時(shí)、資源低占用的需求,具備自主維護(hù)ARP表的能力,支持多設(shè)備級(jí)聯(lián)。該設(shè)計(jì)在高速數(shù)據(jù)采集、遠(yuǎn)距離信息傳輸、片上數(shù)據(jù)高速處理等應(yīng)用場(chǎng)景具有積極的意義。
中圖分類號(hào): TN919
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.222620
中文引用格式: 趙世超,左金印,魏驍,等. 基于FPGA的萬兆以太網(wǎng)UDP協(xié)議通信接口設(shè)計(jì)[J].電子技術(shù)應(yīng)用,2022,48(10):113-117,122.
英文引用格式: Zhao Shichao,Zuo Jinyin,Wei Xiao,et al. Design of 10 gigabit ethernet UDP communication module based on FPGA[J]. Application of Electronic Technique,2022,48(10):113-117,122.
Design of 10 gigabit ethernet UDP communication module based on FPGA
Zhao Shichao,Zuo Jinyin,Wei Xiao,Zhao Zhe
National Computer System Engineering Research Institute of China,Beijing 100083,China
Abstract: In order to solve the rapidly growing data transmission problem for embedded devices, this paper introduces a 10 gigabit UDP/IP protocol communication module, which relies on the Field Programmable Gate Array(FPGA) platform and uses optical fiber as the transmission medium,and explores the impact of introducing the branch prediction mechanism on the transmission delay of the communication interface module. Through in-depth research on the typical transmission model of the existing Open Systems Interconnection(OSI),using hardware description language, the ARP controller, IP controller and UDP controller are modularly designed to form a complete UDP/IP communication module. And the influence of introducing the branch prediction mechanism on the transmission delay of the communication module is evaluated. The analysis shows that the design is simple to implement and adapts to the requirements of embedded devices for high bandwidth, low latency and low resource occupation. It maintains the ARP table independently and supports multi-device cascading. It has positive significance in application scenarios such as high-speed data acquisition, long-distance information transmission, and high-speed processing of on-chip data.
Key words : FPGA;fiber-optic communication;10 gigabit ethernet;UDP/IP protocol;branch prediction

0 引言

    伴隨萬物互聯(lián)時(shí)代的臨近,計(jì)算機(jī)網(wǎng)絡(luò)通信技術(shù)應(yīng)用得到空前發(fā)展,嵌入式電子設(shè)備接入局域網(wǎng)的需求迅速增加。網(wǎng)路傳輸帶寬不斷提高也使得一些特定的領(lǐng)域?qū)?shù)據(jù)傳輸提出了更高的要求。遠(yuǎn)距離通信領(lǐng)域需要更高的數(shù)據(jù)傳輸帶寬和更強(qiáng)的抗干擾能力,用于保障其通信的質(zhì)量和可靠性。工業(yè)生產(chǎn)的數(shù)據(jù)采集系統(tǒng)需要更低的數(shù)據(jù)傳輸延遲和更大的數(shù)據(jù)吞吐容量,用于確保其數(shù)據(jù)的實(shí)時(shí)性和完整性。片上數(shù)據(jù)高速處理領(lǐng)域需要通用化的數(shù)據(jù)傳輸接口,用以增加其可擴(kuò)展性。然而,嵌入式設(shè)備上廣泛使用的CPU和MCU,礙于設(shè)計(jì)體積小、設(shè)計(jì)功耗低等原因,計(jì)算能力的提升速度并不像互聯(lián)網(wǎng)帶寬那樣明顯,并且其差距有進(jìn)一步擴(kuò)大的趨勢(shì)[1]。過高的以太網(wǎng)數(shù)據(jù)傳輸速率會(huì)過度消耗CPU寶貴的計(jì)算資源。在服務(wù)器平臺(tái)上,國外學(xué)者提出的TCP/IP卸載引擎(TCP Offload Engine)技術(shù)是被廣泛接受的解決方案,即使用TOE芯片硬件網(wǎng)卡實(shí)現(xiàn)TCP/IP協(xié)議接口硬件化的技術(shù)來減輕CPU運(yùn)行負(fù)擔(dān)[2]。在嵌入式平臺(tái)上,F(xiàn)PGA從仿真、優(yōu)化到在線調(diào)試都很便捷,在不改變外圍電路的情況下可綜合出不同的電路功能,具有集成度高、設(shè)計(jì)靈活的優(yōu)點(diǎn),成為以太網(wǎng)協(xié)議硬件化平臺(tái)的首選[3]。




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作者信息:

趙世超,左金印,魏  驍,趙  哲

(華北計(jì)算機(jī)系統(tǒng)工程研究所,北京100083)




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