支持多協(xié)議的可配置通信引擎設(shè)計(jì)
電子技術(shù)應(yīng)用
于姝婷1,劉鴻瑾2,張紹林2,施博2
(1.西安電子科技大學(xué) 廣州研究院,廣東 廣州 510555;2.北京軒宇空間科技有限公司,北京100080)
摘要: 針對(duì)國(guó)內(nèi)對(duì)于專用通信引擎的研究空缺,實(shí)現(xiàn)了一種支持多協(xié)議的可配置通信引擎設(shè)計(jì),并以典型的數(shù)據(jù)鏈路層協(xié)議——高級(jí)數(shù)據(jù)鏈路控制(High 1evel Data Link Control, HDLC)協(xié)議的引擎塊實(shí)現(xiàn)為例,采用System Verilog搭建仿真平臺(tái),通過C語(yǔ)言編寫測(cè)試case,以回環(huán)驗(yàn)證的方式保證設(shè)計(jì)正確性??膳渲靡鎵K以自研RSIC核為核心,采用AHB總線互連,內(nèi)部集成HDLC、UART等通信協(xié)議以及DMA、TDM、GPIO等通用外設(shè),實(shí)現(xiàn)通信協(xié)議的處理及數(shù)據(jù)傳輸,有助于解放處理器負(fù)載,提高數(shù)據(jù)處理效率,同時(shí)將HDLC與可配置通信引擎相結(jié)合,解決了多路信號(hào)的HDLC對(duì)處理器資源的占用率高等問題。
中圖分類號(hào):TN492
文獻(xiàn)標(biāo)志碼:A
DOI: 10.16157/j.issn.0258-7998.223528
中文引用格式: 于姝婷,劉鴻瑾,張紹林,等. 支持多協(xié)議的可配置通信引擎設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用,2023,49(7):60-66.
英文引用格式: Yu Shuting,Liu Hongjin,Zhang Shaolin,et al. Configurable communication engine design supporting multiple protocols[J]. Application of Electronic Technique,2023,49(7):60-66.
文獻(xiàn)標(biāo)志碼:A
DOI: 10.16157/j.issn.0258-7998.223528
中文引用格式: 于姝婷,劉鴻瑾,張紹林,等. 支持多協(xié)議的可配置通信引擎設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用,2023,49(7):60-66.
英文引用格式: Yu Shuting,Liu Hongjin,Zhang Shaolin,et al. Configurable communication engine design supporting multiple protocols[J]. Application of Electronic Technique,2023,49(7):60-66.
Configurable communication engine design supporting multiple protocols
Yu Shuting1,Liu Hongjin2,Zhang Shaolin2,Shi Bo2
(1.Guangzhou Research Institute, Xidian University, Guangzhou 510555, China; 2.Beijing SunWise Space Technology Ltd., Beijing 100080, China)
Abstract: In this paper, aiming at the research vacancy of dedicated communication engine in China, a design of configurable communication engine supporting multiple protocols is implemented. Taking the typical data link layer protocol, the engine block implementation of high-level data link control (HDLC) protocol, as an example, the simulation platform is built by System Verilog, and the test case is written in C language to ensure the correctness of the design by loop verification. The configurable engine block takes the self-developed RSIC core as the core, adopts AHB bus interconnection, integrates communication protocols such as HDLC and UART and general peripherals such as DMA, TDM and GPIO, etc., and realizes the processing of communication protocols and data transmission, which helps to free the processor load and improve the data processing efficiency. At the same time, the combination of HDLC and configurable communication engine solves the problem of high utilization rate of processor resources by HDLC with multi-channel signals.
Key words : configurable communication engine;communication controller;high 1evel data link control;data link layer
0 引言
隨著通信處理器對(duì)高帶寬、高性能需求的不斷提高,提高通信系統(tǒng)中嵌入式處理器的數(shù)據(jù)處理能力,減輕處理器負(fù)擔(dān)成為通信處理器考慮的主要因素。目前全球應(yīng)用最廣泛的通信處理器,采用混合架構(gòu),將強(qiáng)大的處理器核心與獨(dú)立的片上通信引擎相結(jié)合,其提供集成的多協(xié)議處理和互通技術(shù),有助于解放PowerPC核心,提高通信數(shù)據(jù)處理效率。但國(guó)內(nèi)對(duì)于可配置通信引擎的研究尚存在較大空缺,故本文立足于集成通信控制器的研究及國(guó)產(chǎn)替代產(chǎn)品的研制,提出了一種支持多協(xié)議的可配置通信引擎設(shè)計(jì)方案,并以高可靠的數(shù)據(jù)鏈路層協(xié)議HDLC模式下的通信數(shù)據(jù)處理為例,完成仿真驗(yàn)證工作。
本文將可配置通信引擎與HDLC控制器相結(jié)合,既可以滿足環(huán)境需求,又能根據(jù)需要對(duì)HDLC接口進(jìn)行配置,解決了多路信號(hào)的HDLC對(duì)處理器資源的占用率高等問題。
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作者信息:
于姝婷1,劉鴻瑾2,張紹林2,施博2
(1.西安電子科技大學(xué) 廣州研究院,廣東 廣州 510555;2.北京軒宇空間科技有限公司,北京100080)
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